This invention is in the field of digital filters, and is more specifically directed to quantization techniques, particularly in infinite impulse response (IIR) digital filters.
As is well known in the art, digital signal processing is now commonly used in many electronic systems, over a wide range of applications. Digital signal processing techniques are now particularly commonplace in telecommunication applications such as wireless telephones, data communications by way of modems and the like, and other facets of this field. Digital signal processing is also utilized in video and audio signal processing, such as used in image recognition, image processing, data compression, digital audio and digital video recording and playback, and the like.
A fundamental building block in the field of digital signal processing is the digital filter. As. is elementary in this field, digital filters refer to the filtering of sampled-data, or discrete-time, signals, which are typically digital representations of analog signals which have been generated by way of analog-to-digital conversion. Fundamentally, a digital filter is a computational process, carried out either through dedicated hardware or through the execution of a sequence of instructions by programmable logic, by way of which an input sequence of numbers is converted into an output sequence of numbers, modified by a transfer function. Typical transfer functions refer to the frequency characteristics of the filter; analogously to analog filter counterparts, examples of digital filter transfer functions include low-pass, high-pass, band-pass, etc. Digital filter computations typically include digital addition, digital multiplication of signal values by constants, and the insertion of delay stages.
As is also well known in the art, digital filters are often classified according to their impulse response. Finite impulse response (FIR) digital filters refer to the class of filters in which only a finite number of input samples affect the generation of a given output sample; typically, FIR digital filters perform computations upon a finite number of input samples (i.e., the current sample, and a selected number of preceding input samples), in a non-recursive fashion. Infinite impulse response (IIR) digital filters are a class of filters in which previous output samples are also used in generating a current output sample, and are thus typically realized in a recursive fashion, including feedback of output sample values. Because of the feedback of prior output values, each current output value of an IIR filter depends upon the value of an infinite series of input sample values, hence the term "infinite impulse response".
As noted above, digital filter realizations generally include multiplication operations, specifically the multiplication of a sampled-data value by a constant value (i.e., a coefficient). According to conventional implementation, a binary multiply of an p-bit digital word by an q-bit digital word will result in a product that occupies p+q-bits. Typically, digital filters operate upon input and output sample values of the same resolution, expressed by the same number of bits in the digital words representing these values. Accordingly, the higher precision data words resulting from the multiply operation are typically truncated, or quantized, to the lower-order of the output sample value. Various types of quantization are known in the art, including simple truncation of lower-order bits, rounding, and magnitude truncation (as will be described in further detail below). In the above example, if p-bits are used to represent the input and output sample values, and if q-bit coefficients are utilized, the p+q-bit multiplication results will be quantized to an p-bit data word.
Quantization necessarily inserts error into the digital filter process, as the resulting quantized value is of less precision that the pre-quantization product. The resulting quantization error is of particular concern in the feedback paths of IIR filters, as will now be described relative to FIGS. 1a and 1b. FIG. 1a illustrates the recursive (feedback) portion of a simple first-order IIR filter 2, realized by adder 3, delay stage 4, and multiplier 5. Adder 3 receives the current input value x.sub.n and the output of multiplier 5 at its inputs, and generates output value y.sub.n at its output. Output value y.sub.n is also applied to delay stage 4, for use in connection with the next sample. The output of delay stage 4 corresponds to output value y.sub.n-1, since delay stage 4 incorporates a delay of one sample period. The output of delay stage 4 is multiplied by coefficient value a, in multiplier 5, and the product applied to adder 3 as noted above. This operation of filter 2 may therefore be defined as: EQU y.sub.n =x.sub.n+ a.multidot.y.sub.n-1
where the nth output sample y.sub.n corresponds to the sum of the current input sample x.sub.n with the product of the value of coefficient a times the prior output sample y.sub.n-1. This simple first order filter thus has the z-domain transfer function H(z): ##EQU1## where z.sup.-1 is the z-domain delay operator. Filter 2 of FIG. 1a thus has a single pole, at z=a, requiring coefficient a to have an absolute value less than or equal to unity for stability.
As noted above, however, for an p-bit input value x (and output value y), and assuming an q-bit coefficient a, the output of multiplier 5 will be an p+q-bit value. As such, some degree (specifically, q-bits) of quantization is necessary to generate the p-bit output sample value y. FIG. 1b illustrates digital filter 2', which is constructed similarly as filter 2 in FIG. 1a, but which also includes quantizer 6 disposed at the output of multiplier 5, prior to adder 3. As shown in FIG. 1b, multiplier 5 generates an p+q-bit product output that is quantized by quantizer 6 into an p-bit digital word prior to application to adder 3. Filter 2' thus generates an p-bit output value y.sub.n for each input sample value x.sub.n. The operation of filter 2' of FIG. 1b can thus be expressed as: EQU y.sub.n =x.sub.n +Q[a y.sub.n-1 ]
where Q refers to the quantization operation of quantizer 6.
A well-known problem in IIR digital filters is referred to as "limit cycles". The limit cycle problem is manifest in digital filters that generate an oscillating output signal in response to a constant or zero-level input. In this regard, FIGS. 1a and 1b include only the recursive portions of filters 2, 2', because limit cycles are caused only by the recursive feedback loops, as is known in the art. It will be understood that the non-recursive (feed-forward) portion of the filters will be implemented in cascade with the recursive portions shown in FIGS. 1a, 1b. Referring to FIG. 1b, an example of the generation of limit cycles responsive to a zero-level input will now be described, in the case where x.sub.n =0 for all n, where a=-1/2, and where y.sub.-1 =7. As noted above, filter 2' of FIG. 1b realizes the expression of y.sub.n =x.sub.n +Q[a .multidot.y.sub.n-1 ]. In this example, assume that the quantization function Q is a simple rounding function Q.sub.R. As a result, and considering that x.sub.n =0 for all n, filter 2' thus may be expressed as: ##EQU2## Beginning with sample n=-1, one may thus tabulate the values of y.sub.n as follows: EQU y.sub.-1 =7 EQU y.sub.0 =Q.sub.R [-1/2(7)]=Q.sub.R [-3.5]=-4 EQU y.sub.1 =Q.sub.R [-1/2(-4)]=Q.sub.R [2.0]=+2 EQU y.sub.2 =Q.sub.R [-1/2(2)]=Q.sub.R [-1.0]=-1 EQU y.sub.3 =Q.sub.R [-1/2(-1)]=Q.sub.R [0.5]=+1 EQU y.sub.4 =Q.sub.R [-1/2(+1)]=Q.sub.R [-0.5]=-1 EQU y.sub.5 =Q.sub.R [-1/2(-1)]=Q.sub.R [0.5]=+1
The -1, +1 sequence for output sample values y beyond y.sub.5 will continue to repeat so long as the zero-level input is applied.
As is evident from the foregoing, oscillation at the output y.sub.n is due to the recursive state signal y.sub.n-1 being initially at a non-zero value, and energized over time by round-off quantizer 6. In effect, round-off quantizer 6 increases the amplitude of the recursive state variable y.sub.n in some instances, keeping this input to filter 2' from decaying to zero, even with input sample values x.sub.n being zero. This limit cycle oscillation at output y.sub.n increases the noise floor of the digital filter, reducing the signal-to-noise ratio of the system. In addition, if the output of the digital filter is applied to downstream digital filter stages, the oscillation error can be unintentionally amplified, exacerbating the error.
Other quantization approaches known in the art address the limit cycle problem. For example, the magnitude truncation quantization approach is defined as: EQU .vertline.Q.sub.MT (x).vertline..ltoreq..vertline.x.vertline., for all x
Mitra and Kaiser, Handbook for Digital Signal Processing (Wiley, 1993), chapter 7. Magnitude truncation effectively rounds off toward zero. For example, in this approach, Q.sub.MT (+3.5)=+3, and Q.sub.MT (-3.5)=-3. As a result, recursive state variables such as y.sub.n-1 in filter 2', will decay to zero with zero-level input values x.sub.n.
By way of extension, second-order IIR digital filters generally also include quantization processes in the recursive, feedback loops. An exemplary simple transfer function, for the recursive portion of the filter only, may be expressed in the z-domain as follows: ##EQU3## In this filter, the coefficients a.sub.1 and a.sub.2 must have absolute values less than 2 and 1, respectively, for purposes of stability (i.e., to avoid the poles of the filter). A non-recursive portion of the filter may, of course, be incorporated into the numerator of this transfer function H(z).
In any event, quantization will be typically utilized in typical digital realizations, as will now be described relative to FIGS. 2a and 2b, which illustrate alternative approaches in implementing quantization into second-order IIR digital filters.
In FIG. 2a, filter 8 includes adders 10 and 20. Adder 10 receives the current input sample value x.sub.n and the output of adder 20 at its inputs, and generates current output sample value y.sub.n at its output. Output sample value y.sub.n is fedback into filter 8 by way of delay stages 11, 13, each of which encompass a delay defined by the sample period of filter 8; the output of delay stage 11 is applied to the input of delay stage 13, as shown. Sample y.sub.n-1 at the output of delay stage 11 is applied to multiplier 12, and is multiplied by coefficient a.sub.1 thereby; similarly, sample y.sub.n-2 at the output of delay stage 13 (and which thus has been delayed by two sample periods) is applied to multiplier 14, which multiplies sample y.sub.n-2 by coefficient a.sub.2.
As noted above, the output of multipliers 12, 14 are p+q-bit digital words, in the case where input and output samples x, y are p-bit words and where coefficients a.sub.1, a.sub.2 are q-bit words. In filter 8 of FIG. 2a, two quantizers 16, 18 are utilized at the outputs of multipliers 12,14, respectively, and their outputs (p-bits wide) are added by adder 20, the output of which is applied to adder 10. The operation realized by second-order IIR digital filter 8 may be expressed as: EQU y.sub.n =x.sub.n +Q[a.sub.1 y.sub.n-1 ]+Q[a.sub.2 y.sub.n-2]
This expression reflects the two quantizers 16, 18.
In FIG. 2b, filter 8' includes a single quantizer 24 is inserted between adder 22 and adder 10. The filter expression of filter 8' is as follows: EQU y.sub.n =x.sub.n +Q[a.sub.1 y.sub.n-1 +a.sub.2 y.sub.n-2]
As described in Bauer and Leclerc, "Computer-Aided Test for the Absence of Limit Cycles in Fixed-Point Digital Filters", Transactions on Signal Processing (IEEE, Nov. 1991), pp. 2400-2410, the stability region within which coefficients a.sub.1, a.sub.2 may reside is greater for filter 8' than for filter 8. Specifically, coefficient a.sub.1 may not have an absolute value greater than 1 for any value of coefficient a.sub.2 in filter 8, while in filter 8' coefficient a.sub.1 may have an absolute value greater than 1 for some negative values of coefficient a.sub.2 (particularly as coefficient a.sub.2 becomes more negative, up to its limit of -1). Accordingly, filter 8' is often preferred, as a wider range of filter characteristics are available.
However, adder 22 receives the full precision results of multipliers 12, 14, and as such is realized as an p+q-bit adder according to conventional techniques. FIG. 3 illustrates the operation of multipliers 12, 14 and adder 22 in this example. As illustrated in FIG. 3, multiplier 12 is realized as a series of successive shift and add operations applied to output sample value y.sub.n-1 from delay stage 11, in the manner defined by the non-zero bits of coefficient a.sub.1, with the final sum a.sub.1 y.sub.n-1 being expressed as p+q-bits. Multiplier 14 is similarly arranged, and multiplies output sample value y.sub.n-2 by coefficient a.sub.2. Adder 22 adds the two results from multipliers 12, 14, to derive the p+q-bit value a.sub.1 y.sub.n-1 +a.sub.2 y.sub.n-2.
While improved quantization is provided by the use of single quantizer 24 of filter 8', in combination with the wider range of coefficients a.sub.1, a.sub.2 under which stability is still maintained, the higher precision implementation of adder 22 occupies a significantly greater amount of chip area, particularly if filter 8' is replicated many times in an integrated circuit, for example in realizing higher order filters by the cascading of first and second order filters. Additionally, while quantization error is improved by high precision adder 22 in filter 8', a certain amount of noise is generated by adder 22 itself in a manner which depends upon the number of bits of precision.